Recently, so-called buildup multilayer wiring board is noticed from a demand for high densification of a multilayer wiring board. The buildup multilayer wiring board is manufactured by a method disclosed, for example, in JP-B-4-55555. That is, an insulating material made of a photosensitive adhesive for electroless plating is applied onto a core substrate having conductor circuits, dried, exposed to a light and developed to form an interlaminar insulating layer having an opening for via-hole. Then, the surface of the interlaminar insulating layer is roughened by a treatment with an oxidizing agent or the like and a plating resist is formed on the resulting roughened surface and thereafter portions not forming the resist are subjected to an electroless plating to form a two-layer conductor circuit pattern including a via-hole. Such steps are repeated plural times to obtain a multilayered buildup wiring board.
And also, a multilayer technique using so-called RCC (RESIN COATED COPPER) is watched as the buildup multilayer printed wiring board. This technique is a technique wherein RCC is laminated on a circuit board and copper foil is etched to from an opening in a position for the formation of a via-hole and a laser beam is irradiated to the opening portion to remove a resin layer and the opening portion is plated to form a via-hole.
Furthermore, there is developed a multilayer technique wherein one-sided circuit boards having a conductive substance filled in a through-hole are laminated through an adhesive layer as described in JP-A-9-36551.
In such a multilayer printed wiring board, a surface of an underlayer conductor circuit is roughened for improving an adhesion property between the surface of the underlayer conductor circuit and the interlaminar resin insulating layer. The thus formed roughened layer can improve the adhesion property in a via-hole portion. Such a roughening is carried out by graphitization-reduction treatment, etching with sulfuric acid-hydrogen peroxide, plating of copper-nickel-phosphorus needle alloy and the like.
The printed wiring board is provided on its surface layer with solder bumps and connected to an IC chip through the solder bumps. In this case, a solder resist layer is formed in the printed wiring board to protect the conductor circuit for solder pad as a surface layer and so as not to fuse solder bumps with each other.
In the printed wiring board, the surface of the conductor circuit is subjected to a roughening treatment for enhancing the adhesion between the conductor circuit for solder pad and the solder resist layer. As the roughening treatment of the conductor circuit, there are used graphitization-reduction treatment, etching with sulfuric acid-hydrogen peroxide, plating of copper-nickel-phosphorus needle alloy and the like.
However, it is known that when the via-hole is formed by plating, the plated film hardly adheres to the roughened layer and it is apt to cause the peeling of via-hole conductor. For this end, it becomes common sense that although the roughened layer is formed on the surface of the underlayer conductor circuit in portions contacting with the interlaminar resin insulating layer, the roughened layer is removed in portions contacting with the via-hole conductor (see, for example, JP-A-3-3298).